The present invention relates to integrated circuit devices, and more particularly, to transistor structures for integrated circuit devices.
As integrated circuits have been highly integrated, shallow trench isolation (STI) has replaced local oxidation of silicon (LOCOS) for isolating active regions, e.g., source and drain regions for transistors. However, the reduced area used for transistors can result in reduction of the threshold voltage Vth of the transistor. Such a phenomenon is called the “inverse narrow width effect,” which is illustrated in FIG. 1.
Known causes of inverse narrow width effect include boron segregation and electric field crowding occurring at the edges of an active region defined by STI. FIG. 2 is a view of the layout of a gate pattern 7 formed across an active region 3 and FIG. 3 is a cross-sectional view of the gate pattern 7 of FIG. 1, taken along the lines III-III′. When a gate oxide layer 4 is regrown after STI regions 2 are formed in a substrate 1 to define an active region 3, boron ions 5, which have been doped on the substrate 1 to form a channel, are typically transferred to a gate oxide layer 4. As a result, the density of the boron ions 5 at edge regions E of the active region 3 may decrease, thereby lowering a threshold voltage of a transistor. This phenomenon is referred to as boron segregation.
When voltage is applied to the gate 7 to operate the transistor, an electric field is established in the gate oxide layer 4 in both horizontal and vertical directions due to the presence of recesses R in the STI region 2. This can lead to a concentrated electric field near the edge regions E, which can reduce the threshold voltage of the transistor. This is referred to as electric field crowding. As shown in curve a of FIG. 4, the threshold voltage of the edge region E (normalized to 100 in FIG. 1) may be reduced 20% due to boron segregation and electric field crowding.
Referring to FIG. 5, for a transistor of a highly integrated DRAM, portions 7a of gate lines referred to as “access gates” are disposed on an active region 3 and have a length E that is sufficient to operate the transistors. Other gate line portions 7b referred to as “pass gates” are formed on STI regions, and have a gate length L′ sufficient to propagate signals. In an actual device, limitations of the photolithography process used to fabricate the device may cause the gate length at a region E to be significantly shorter than the gate length at a region C, as indicated by dashed lines in FIG. 5. As a result, as shown in curve b of FIG. 4, the threshold voltage of a transistor at the region E can be reduced as much as to 60% in comparison to the threshold voltage at the region C. This can result in undesirably large sub-threshold leakage currents, and can deteriorate the dynamic refresh characteristics of the DRAM.